1. Field of the Invention
The present invention relates to a bias voltage generating circuit for generating a bias voltage of a drive circuit for activating a liquid crystal panel or the like, more specifically to a bias voltage generating circuit capable of turning off in a power-saving state and returning from the power-saving state to an operation state at a high speed.
2. Description of the Related Art
In recent years, a liquid crystal panel has been applied to various devices in a broader range including large-size devices and small-size devices such as a mobile telephone, there has been an increasing demand for reduction of power consumption in response to circumstances. An effective method in order to reduce the power consumption is that a liquid crystal drive circuit leaves an output circuit in a halting state during a blanking period, which is a non-display period, so that a steady-state current is zeroed (hereinafter, referred to as power saving processing). Another preferable method for reducing the power consumption is to increase in frequency of the power saving processing. In order to increase in frequency of the power saving processing, it is important to speed up a returning process from a power-saving state to an operation state.
Below, a bias voltage generating circuit and a drive output circuit are described according to a conventional technology, an example of which is recited in U.S. Pat. No. 6,930,543, referring to FIG. 1. FIG. 1 is a circuit diagram illustrating a bias voltage generating circuit of an operational amplifier for driving the liquid crystal and a drive output circuit whose output number is n according to the conventional technology. The description is given below based on an example in which the drive output number is n.
A reference numeral 100 shown in FIG. 1 denotes a bias voltage generating circuit. The bias voltage generating circuit 100 comprises a reference voltage generator 20 and a standby voltage generator 30. The reference voltage generator 20 comprises P-channel MOS transistors MP1, MP2 and MP3, N-channel MOS transistors MN1 and MN2, and a resistance R1. The standby voltage generator 30 comprises a switch SW1 connected between a ground voltage and a bias voltage Vbiasn. The bias voltage generating circuit 100 thus constituted has a function of outputting the bias voltage Vbiasn of NMOS transistors for a constant current source in operational amplifiers A1(1)-A1(n) for driving the liquid crystal. In the drawing, C1n(1)-C1n(n) denotes a wiring capacitance respectively.
An operation of returning the bias voltage generating circuit 100 from a power-off state is described referring to a timing chart shown in FIG. 2. A power save signal PS is set to a non-active state “high” in a T1 period where a main power is in ON state. Therefore, the P-channel MOS transistor MP3 of the reference voltage generator 20 is turned off, while the N-channel MOS transistor MN1 thereof is turned on.
At the time, the P-channel MOS transistor MP1, resistance R1 and N-channel MOS transistor MN1 of the reference voltage generator 20 generate a reference current Iref1. A current mirror circuit comprising the P-channel MOS transistors MP1 and MP2 generates a reference current Iref2. The N-channel MOS transistor MN2 diode-connected to the P-channel MOS transistor MP2 generates the bias voltage Vbiasn based on the reference current Iref2. The bias voltage Vbiasn is supplied to input capacitances of the operational amplifiers A1(1)-A1(n) for driving the liquid crystal and wiring capacitances C1n(1)-C1n(n). The T1 period is a period when output control switches SW10(1)-SW10(n) of outputs Vout(1)-Vout(n) of the operational amplifiers for driving the liquid crystal are set to ON.
The output control switches SW10(1)-SW10(n) are turned off in a T2 period where a first sub power is in ON state, while any other control operation is the same as that of the T1 period. When the output control switches SW10(1)-SW10(n) are turned off and simultaneously the power save signal is set to an active state “Low”, the output voltages of the operational amplifiers A1(1)-A1(n) for driving the liquid crystal are thereby influenced. Therefore, the T2 period (first sub power ON state) is provided as an overlapping period (non-active state “high”).
In a T3 period that is a power OFF state, as the power save signal PS is set to the active state “Low”, the P-channel MOS transistor MP3 of the reference voltage generator 20 is turned on, while the N-channel MOS transistor MN1 is turned off. In other words, the reference current Iref1 is “0” so as to be the power OFF state. At the time, as the switch SW1 for controlling the standby voltage output is set to ON, the bias voltage Vbiasn is thereby “low”.
In a T4 period that is a second sub power ON state, the switch SW1 for controlling the standby voltage output is turned off, and the output control switches SW10(1)-SW10(n) are also set to OFF. During the period, the bias voltage Vbiasn returns to a predetermined voltage, and the restoring operation is then completed.
In a T5 period that is the main power ON state, the switch SW1 for controlling the standby voltage output is turned off, while the output control switches SW10(1)-SW10(n) are turned on. Thereby, the operational amplifiers A1(1)-A1(n) for driving the liquid crystal output the Vout(1)-Vout(n) at a predetermined voltage level.
In the conventional bias voltage generating circuit, the small reference current Iref2 generated by the P-channel MOS transistor MP2 and the N-channel MOS transistor MN3 is used to charge the input capacitances of the operational amplifiers A1(1)-A1(n) for driving the liquid crystal and the wiring capacitances C1n(1)-C1n(n), so that the bias voltage returns to the predetermined voltage.
In recent years, the number of the operational amplifiers A1(1)-A1(n) for driving the liquid crystal is increased based on a large-screen and a higher image quality of the liquid crystal panel. More specifically, the input capacitances of the operational amplifiers A1(1)-A1(n) for driving the liquid crystal and n of the wiring capacitances C1n(1)-C1n(n) are increased, which makes it necessary to supply a large capacitance value with a small current. As a result, it becomes impossible for the bias voltage to return within a predetermined time frame.
Though it is possible to make bias voltage return within the predetermined time frame by increasing the reference current Iref2 of the bias voltage generating circuit, however, it results in the large increase of the power consumption.